In the fabrication of a metal-oxide-semiconductor (MOS) device, the gate integrity of the dielectric material is a key factor in determining the long term reliability characteristics of the device. In an MOS transistor, the gate dielectric material must support a substantial voltage difference between the gate electrode and the semiconductor substrate. The gate dielectric material must also maintain its ability to support the voltage difference between the gate and the substrate, while being subjected to the electron and hole injection from both the gate electrode and the substrate. In the case of very-large-scale-integration (VLSI) devices, the effective gate lengths are on the order of less than 1 micron. At such small effective gate lengths, electrons can be injected into the dielectric layer during periods when the transistor in switched on and off. The injection of electrons into the dielectric material can, over time, cause a shift in the threshold voltage of the transistor. Over an extended period of time, a continual shift in the threshold voltage eventually results in an inability to switch the transistor on and off. Therefore, it is important in the fabrication of an MOS transistor that a high quality dielectric material be provided in order to insure long term reliability of the transistor.
A similar need for a high reliability dielectric material is realized in the fabrication of electrically-erasable-programmable-read-only memories (EEPROMs). An EEPROM cell varies charge stored on a floating gate in order to vary the threshold voltage, V.sub.T, of a floating gate type MOS transistor. In the case of a FETMOS EEPROM device, the device is said to be "programmed" when the V.sub.T of the transistor is less than some predetermined switch point voltage, V.sub.TSP. Correspondingly, the device is said to be "erased" when the V.sub.T of the device is greater than V.sub.TSP. Typically, V.sub.TSP is chosen to be less than the positive supply voltage V.sub.DD in static memory arrays, and is approximately equal to V.sub.DD in dynamic memory arrays. Making the charge stored on the floating gate more positive decreases the V.sub.T of the transistor, and making the charge stored on the floating gate more negative increases V.sub.T of the transistor. Charge is added to or removed from the floating gate by Fowler-Nordheim tunneling, channel hot carrier injection, or other techniques.
The ability to perform programming and erasing of an EEPROM device depends on the maintenance of a threshold voltage difference as the charge on the floating gate is changed from positive to negative. An EEPROM device which relies on electron tunneling for programming and erasing is known in the art as a floating-gate electron tunneling MOS (FETMOS) EEPROM. Typically, a region in the dielectric material underlying the floating gate is especially fabricated for the purposes of electron tunneling between the floating gate and the substrate. The dielectric layer through which the electron tunneling occurs, must, necessarily, be very robust to insure the long term programmability of the EEPROM device.
In the search for more robust dielectric materials, researchers have turned to oxynitride materials. Oxynitrides have demonstrated excellent endurance to electron and hole injection over prolonged periods of time. The endurance of oxynitride is thought to be related to the accumulation of nitrogen near the silicon-silicon dioxide (Si/SiO.sub.2) interface.
Several techniques have been developed for the formation of an oxynitride dielectric material. In one method, silicon dioxide is formed by thermal oxidation of a silicon substrate. Then, a polysilicon layer is deposited to overlie the silicon dioxide layer, and implanted with nitrogen. Next, an anneal step is used to drive the nitrogen from the polysilicon layer to produce increased concentrations of nitrogen at the silicon dioxide interfaces ("Improvement of Thin-Gate Oxide Integrity Using Through-silicon-Gate Nitrogen Ion Implantation," S. Haddad, et al., IEEE, Electron Dev. Letters, (EDL-8), 2, 1987, pp. 58-60). In another method, ammonia is used to increase the interfacial nitrogen concentration in a previously formed oxynitride layer ("MOS Characteristics of NH.sub.3 -Nitrided N2O-Grown Oxides," G. W. Yoon, et al., IEEE, Electron Dev. Letters (14), 4, 1993, pp. 179-181). In yet another method, oxynitride is formed by subjecting a silicon substrate to rapid thermal annealing in a nitrous oxide ambient ("High-Performance Scaled Flash-Type EEPROMs with Heavily Oxynitrided Tunnel Oxide Films," H. Fukuda, et al., IEEE, IEDM 1992, pp. 465- 466). While the foregoing techniques are effective for the formation of an oxynitride material, a nitrogen rich layer is only obtained at a silicon silicon-dioxide interface. To obtain the enhanced dielectric endurance required by VLSI MOS devices, such as MOS transistors and FETMOS EEPROM devices, and the like, further development is necessary to enhance the charge-to-breakdown value of oxynitride dielectric material.